In a conventional static random access memory (SRAM) design, the bit lines are biased at the voltage level of V.sub.CC, or nearly this level. In some designs, the bit lines have pull-up transistors of the PMOS type, which pull the bit line voltage to V.sub.CC, and in other designs, a NMOS transistor is used for pull-up, in which case the bit lines are pulled up to V.sub.CC -V.sub.TM. The bit line pull-up transistors are gated by a signal which is active during the read cycle. In addition, a bit line equalization device, which is normally a PMOS transistor, is gated by a signal generated from an address transition detector circuit.
During pull down, the slew rate of the voltage level applied to the bit line with respect to time, is the quotient of the bit line current divided by the bit line capacitance. The bit line current is EQU I.sub.CELL -I.sub.BLPU
where I.sub.CELL is the cell current, and I.sub.BLPU is the bit line pull-up current. It is apparent from this relationship that the slew rate can be made fast if the bit line pull-up current is low, with a higher R.sub.ON, the ON resistance of the bit line pull up devices. However, the maximum difference in the voltage levels of the bit lines then becomes larger, which requires more time for bit line equalization, since R.sub.ON, is greater. Accordingly, in conventional SRAM design, the bit line pull-up transistors are typically optimized so the total time of the bit line equalization and the bit line signal development time, combined, is a minimum.